Semiconductor integrated circuits, such as large scale integrated circuits (LSIs), each include an interface for data transmission, which includes at least one of a transmission circuit and a reception circuit. This interface is used for short-distance data communication performed inside the LSI, performed with another LSI mounted on the same circuit board, and so forth. The interface included in the LSI is also used for long-or-middle-distance data communication performed with another circuit board, performed with a daughter card connected to a circuit board having this LSI mounted thereon via a backplane, performed between a server including a circuit board having this LSI mounted thereon and another server, and so forth.
To improve the transmission accuracy of data transmission, it is desirable that an output impedance of a transmission circuit, a characteristic impedance of a transmission line, and an input impedance of a reception circuit match one another. Accordingly, there has been proposed an output buffer circuit in which a bridge circuit including switches that are switched in accordance with data to be transmitted is provided between a transmission line and a power supply and in which the bridge circuit and the power supply are connected to each other via an impedance element.
In this proposal, a replica of the output buffer circuit is provided. An output impedance of the replica is adjusted to match the characteristic impedance of the transmission line. Based on this adjustment result, an impedance of the output buffer circuit is adjusted. In this way, the output impedance of the output buffer circuit is adjusted to match the characteristic impedance of the transmission line in the above proposal.
Recently, a higher data transmission speed and a lower power consumption have been demanded. Accordingly, there has been proposed a configuration in which a plurality of differential output circuits are connected in series between a power supply line and a ground line. With this configuration, for example, by connecting three differential output circuits in series, the power consumption is reduced to ⅓ of the power consumed when power is individually supplied to the differential output circuits.
Differential transmission circuits that operate in accordance with current mode logic (CML) are typical transmission circuits to be connected to transmission lines. Output impedances of these differential transmission circuits are determined by resistances of terminating resistors that are connected to transistors. It is therefore difficult to adjust the output impedances.
Accordingly, there has been proposed an interface circuit that operates in accordance with CML and that includes a terminating resistor circuit using a symmetric load which includes a pair of transistors having the same conductivity type and a terminating resistor circuit using a transfer gate. In this proposal, the output impedance is adjusted by selectively using the terminating resistor circuit that uses a symmetric load and the terminating resistor circuit that uses a transfer gate.
The related art is described, for example, in Japanese National Publication of International Patent Application No. 2001-500326, Japanese Laid-open Patent Publication No. 2009-200651, and Japanese Laid-open Patent Publication No. 2002-185300.
However, in transmission circuits that operate in accordance with CML, it is desirable that a certain current flows through transistors serving as current sources. This makes it difficult to reduce the power consumption of the transmission circuits.